How to analyze the timing of UART Transmission based on FPGA
How to analyze the transmission timing of UART based on FPGA? aiming at this problem, this article introduces the corresponding analysis and solution in detail, hoping to help more partners who want to solve this problem to find a more simple and feasible method.
The following is the main content of this section:
Serial port transmission data is a frame of 11 bits, refer to the serial port timing in https://blog.csdn.net/Pieces_thinking/article/details/99234401.
figure 2 33 serial port timing
Table 2 7 Serial Port timing description Table
The "high level" of on the serial bus is the default state. When the transmission of a frame of data begins, the level must be lowered first, which is the function of bit 0. Bit 0 is followed by eight data bits, which are the most meaningful things in a frame of data. The last two bits are the check bit and the stop bit, which function like naming.
Another important parameter of serial port transmission is "baud rate". Macroscopically, "baud rate" is the transmission speed of serial port transmission; microscopically, "baud rate" is the "period of one bit" in serial port transmission, in other words, it is also "the time spent by one bit". This concept is important in programming at a later stage.
The baud rates commonly used in are 9600 bps and 115200 bps (bit per second). "9600 bps" means that 9600 bits can be transmitted per second. However, the "period of a bit" calculated by the formula will be exposed.
Period of one bit = 1 / bps
= 1 / 9600
= 0.00010416666666666667
from the above formula, we understand the fact that 9600 bps takes 0.000104166666666667s to transmit one bit of data. If it is a frame of 11-bit data, you need to
0.0001041666666666666667 x 11 = 0.0011458333333333334
can transmit in a second.
1 / 0.00114583333333334 = 872.727272727268
872.727272727268 frames of data.
of course this is just a numerical calculation, but there are actually a lot of invisible delay factors.
when using 115200 bps
Period of one bit = 1 / bps
= 1 / 115200
= 0.00008680555555555555555555555555555555555555
It takes 0.000086805555555555555556s for to transfer one bit data. If it is a frame of 11-bit data, you need to
0.00008680555555555555556 x 11 = 0.000954861111111111111111111111
can transmit in a second.
1 / 0.0009548611111111111111111111111111 = 1047.272727272727272739459174
1047.27272727272727272 frame data.
If is quantized with the clock rate of 50Mhz:
(1max 115200) / (1/50E+6) = 8.68E-6 / 20E-9
= 434
This is the answer to the question on how to analyze the timing of UART transmission based on FPGA. I hope the above content can be of some help to you. If you still have a lot of doubts to be solved, you can follow the industry information channel for more related knowledge.
