How to force the top level of IP to be specified in Vivado

This article is to share with you about how to specify the top level of IP in Vivado. The editor thinks it is very practical, so I share it with you to learn. I hope you can get something after reading this article.

In the IP Integrated interface, create a new GROUP under Advance. The name does not matter. You can set any name. The default name is Verilog Synthesis Wrapper.

Modify the IP File Group Properties of this Group (you can click on the Group you just created, there will be a property bar):

Name is xilinx_verilogsynthesiswrapper

Env ids is verilogSource:vivado.xilinx.com:synthesis.wrapper or: vivado.xilinx.com:synthesis.wrapper

Type is verilog:synthesis_wrapper

The above is the Top layer when the synthesis is established. Here is how to set the top layer of IP for simulation:

Also create a new GROUP under Advance. The name can also be set at will. Default is Verilog Simulation Wrapper.

Modify the operation under IP File Group Properties (this is the same as the comprehensive operation above):

Name is xilinx_verilogsimulationwrapper

Env ids is verilogSource:vivado.xilinx.com:simulation.wrapper or: vivado.xilinx.com:simulation.wrapper

Type is verilog:simulation_wrapper

Then add the _ v.ttcl as the top level (the moudule name must be defined with module) to the two Group, and Vhdl is the same In fact, you can also add Verilog files, but this does not make sense, ttcl files play a strong advantage, such as code reduction, for example, I need to set n groups of variables, variables named a0mema1da2dai3.an (n > 100), with verilog absolutely can not be achieved with no more than 10 lines of code, but ttcl can.

The above is how to specify the top level of IP in Vivado. The editor believes that there are some knowledge points that we may see or use in our daily work. I hope you can learn more from this article. For more details, please follow the industry information channel.