What is the Verilog HDL implementation of CRC16 encoder
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The generating polynomial used in CRC-16 code is
G (x) = x16 + x15 + x2 + 1
Module crc_16 (
Clk,rst,x,crc_reg,crc_s
);
Input clk
Input rst
Input XTX Universe serial input
Output [15:0] crc_reg
Output crc_s;//the synchronous signal
Reg [15:0] crc_reg
Reg [3:0] count
Reg crc_s
Wire [15:0] crc_enc
Always @ (posedge clk)
Begin
If (! rst)
Begin
Crc_reg
