Debugging of SPI Communication on encryption Chip
SPI is the abbreviation of Serial Peripheral Interface (Serial Peripheral Interface). It is a synchronous serial interface technology developed by Motorola Company. It is a high-speed, full-duplex, synchronous communication bus.
The communication principle of SPI is very simple, it works in a master-slave mode, which usually has one master device and one or more slave devices, and requires at least four lines: SDI (data input), SDO (data output), SCLK (clock), and CS (chip selection).
(1) SDO/MOSI-- master device data output, slave device data input
(2) SDI/MISO-- master device data input, slave device data output
(3) SCLK-- clock signal, generated by the main equipment
(4) the CS/SS-- slave device enable signal, which is controlled by the master device.
It is not difficult to understand CS as a chip selection signal. When a plurality of slave devices are hung on the bus, the host can activate the device and complete the communication with the device by controlling the chip selection signal of the corresponding slave device. Generally, the film is selected as a low power level and is in a selected state.
It should be noted that there are four different modes of SPI communication, and different slave devices may be configured as a certain mode at the factory, which cannot be changed; but both sides of our communication must work in the same mode, so we can configure the SPI mode of our master device to control the communication mode of our master device through CPOL (clock polarity) and CPHA (clock phase), as follows:
Mode0:CPOL=0,CPHA=0
Mode1:CPOL=0,CPHA=1
Mode2:CPOL=1,CPHA=0
Mode3:CPOL=1,CPHA=1
The clock polarity CPOL is used to configure which state the level of the SCLK is in when it is idle or effective, and the clock phase CPHA is used to configure the edge where the data sampling is.
As a special application of encryption chip, most of its SPI communication uses the standard SPI interface protocol, but there is no lack of exceptions. There are some points to pay attention to during debugging:
1. As an anti-piracy function module or a data encryption and decryption module, most of the encryption chips need to be used as SPI slave devices, and the upper computer as the SPI host.
2. The host SPI is set to CKPOL=0 and CKPHA=0. Its meaning: when the time and space is idle, the SCLK is at the low level, and the data sampling is at the first edge, that is, the SCLK jumps from the low level to the high level, so the data sampling is on the rising edge and the data transmission is on the falling edge.
3. Some encryption chips have special protocols, and because SPI does not have the function of synchronous signals, the encryption chips need to send notification signals to the host with the help of BUSY pins. When the BUSY is high, the SPI host device is allowed to send data, on the contrary, it allows the host to receive data.
4. BUSY is the SPI request signal. When the BUSY is pulled down, the SPI host device is allowed to read the data, and the SPI host side pulls the CS/SS down, and the SPI_CLK generates a clock.
5. When the chip fails, it can be reset by reset.
