How to understand checker in Testbench

This article is to share with you about how to understand checker in Testbench. The editor thinks it is very practical, so I share it with you. I hope you can get something after reading this article.

In a test platform, it is useful to check the behavior of DUT from within. VCS provides two mechanisms: assert and expect structures. As follows:

[label:] assert (expression) [action block] [else statement]

[label:] expect (property spec) [action block]

[else statement]

You can use the assert structure to check the behavior of the current simulation time and the expect structure to check the behavior of multiple clock cycles.

For example, in the FIFO test platform, fifo_reset_check () task checks to determine if the output of DUT is correctly reset within a specified period of time:

Fifo_reset_check () task first checks that empty is set in the first two clock cycles. If empty is not set within two cycles, VCS issues the following validation error:

Error: "fifo_test.v", 94:

Fifo_test_top.test.fifo_reset_check.E1: at time 350

All validation checks should have label to facilitate debugging. The E1:expect statement prevents task from performing the next line of code checking until success or error. The next five A * lines of code immediately check to see if the other output signals are correctly set by DUT.

This is how the checker in Testbench is understood. The editor believes that there are some knowledge points that we may see or use in our daily work. I hope you can learn more from this article. For more details, please follow the industry information channel.