Pin difference between serial port SRAM and parallel port SRAM

First of all, let's take a look at the difference between parallel and serial ports:

The difference between pins:

Serial port SRAM (or other memory) usually has the following schematic diagram:

Serial port SRAM pin

There are only less than 8 pins in SCK,CS#,SI,SO,HOLDB,VCC,VSS, which generally follow the SPI protocol.

There are many parallel SRAM pins and few serial SRAM pins.

Most of the SRAM is operated by parallel port (parallel), and a few exotic ones are operated by serial port protocol. The SRAM of parallel port usually has the following schematic diagram:

Parallel port SRAM pin

There are nearly 50 pins, including address, IO, enable signal, power supply and so on.

The address is usually related to the capacity. Here is the capacity of the 1Mb. There are 16 addresses (A15-A0).

Where IO is usually a multiple of 8, here are 16 (IO15-IO0)

Enable signal CE#,WE#,OE#,BHE#,BLE#, Please forgive me for using # instead of overlining, which cannot be entered at all, MD

Power signal: VCC/VSS.

The difference of circuit classification

Parallel port SRAM is an asynchronous circuit with no clock signal.

Serial port circuit is a synchronous circuit, sometimes clock signal.

Let's take a look at the application of parallel port SRAM.

Parallel port SRAM is usually fast and is used in many high-speed situations, such as cache memory (Cache) as CPU, as shown in the following figure:

SRAM is at the top of the pyramid of computer memory. In terms of speed, SRAM > DRAM > NAND. Because the operating conditions of SRAM are relatively simple, it is a simple process of opening MOS tubes, fighting each other or transmitting values, which can be realized with core voltage. If DRAM produces about 3v high voltage, the operating voltage of NAND is even higher.

In terms of area, the six tubes (6T) of the SRAM memory cell are the largest compared to the 1T1C of DRAM and the 1T of NAND. So the price is also SRAM > DRAM > NAND.

Sometimes SRAM will be used as a substitute for registers, because the area of SRAM storage cells (6 tubes) is much smaller than that of registers (DFF). If hundreds of Byte are used in the design, the area of registers may be several times larger than SRAM.