Detailed explanation of clock Frequency Modification of SylixOS based on ZYNQ

Overview

Taking the ZYNQ7000 platform as an example, this document describes in detail how to modify the clock frequency of ZYNQ.

Clock frequency modification process

The clock rate modification process for ZYNQ7000, as shown in figure 2.1. The specific steps are as follows:

Step 1: release the register write lock of ZYNQ7000

Step 2: write the PLL octave value and PLL configuration parameters we need to set to the corresponding register

Step 3: perform bypass mode conversion and software restart of PLL to make the PLL octave value and PLL configuration parameters we just set take effect.

Step 4: put the register in the write-locked state again.

Figure 2.1Flowchart of clock rate modification for ZYNQ7000

The specific code implementation of ZYNQ7000's ARM_PLL_CLK clock frequency modification is shown in listing 2.1of the program. The way of unlocking and locking write lock may be different in different platforms. For ZYNQ7000 platform, it is necessary to write 0xDF0D to SLCR_UNLOCK register to release write lock. Writing 0x767B to SLCR_LOCK register can invalidate the write operation of related registers.

The clock rate modification code for the program listing 21 ZYNQ7000

/ * function name: zynqPllFeedBackSet** function Description: zynq ARM_PLL_CLK clock frequency doubling setting * * input: NONE** output: NONE** return: NONE**** * * / VOID zynqPllFeedBackSet (VOID) {UINT32 uiClkCtrl UINT32 uiFeedBackDiv; UINT32 uiNum; uiNum = read32 (ZYNQ_SLCR + SLCR_LOCKSTA); if (0! = uiNum) {write32 (SLCR_UNLOCK_MAGIC, ZYNQ_SLCR + SLCR_UNLOCK); / * write 0xDF0D, unlock write * / uiNum = 0;} / * * set the octave value of ARM_PLL * / uiClkCtrl = read32 (ZYNQ_SLCR + ARM_PLL_CTL) UiFeedBackDiv = uiClkCtrl & ~ XZYNQ_SLCR_ARM_PLL_CTRL_PLL_FDIV_MASK; uiFeedBackDiv | = (SLCR_FEED_BACK_DIV_VALUE