What is the supporting method for independent compilation of makefile modules?

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The solution is: 1, the module name (module) as the target name (pseudo target) to establish rules; 2, the target (module) corresponding to the dependency for build build/module;3, rules in the command into the corresponding module folder for compilation; 4, the compilation results are stored in the build folder. The key technical point is how to get the module name specified in the make command line, through the predefined variable: $(MAKECMDGOALS), the target name specified on the command line (the command line parameter of make). As follows

Let's take a look at how the specific makefile is written. Change the pro-rule.mk in the previous blog to the following

.PHNY: all compile link clean rebuild $(MODULES) DIR_PROJECT: = $(realpath.) DIR_BUILD_SUB: = $(addprefix $(DIR_BUILD) /, $(MODULES)) MODULE_LIB: = $(addsuffix .a, $(MODULES)) MODULE_LIB: = $(addprefix $(DIR_BUILD) /, $(MODULE_LIB)) APP: = $(addprefix $(DIR_BUILD) /, $(APP)) all: compile $(APP) @ echo "Success! Target = > $(APP) "compile: $(DIR_BUILD) $(DIR_BUILD_SUB) @ echo" Begin to compile... "@ set-e;\ for dir in $(MODULES) \ do\ cd $$dir & &\ $(MAKE) all\ DEBUG:=$ (DEBUG)\ DIR_BUILD:=$ (addprefix $(DIR_PROJECT) /, $(DIR_BUILD))\ DIR_COMMON_INC:=$ (addprefix $(DIR_PROJECT) /, $(DIR_COMMON_INC))\ CMD_CFG:=$ (addprefix $(DIR_PROJECT) / (CMD_CFG))\ MOD_CFG:=$ (addprefix $(DIR_PROJECT) /, $(MOD_CFG))\ MOD_RULE:=$ (addprefix $(DIR_PROJECT) /, $(MOD_RULE)) & &\ cd. ;\ done @ echo "Compile Success!" Link $(APP): $(MODULE_LIB) @ echo "Begin to link..." $(CC)-o $(APP)-Xlinker "- (" $^-Xlinker "-)" $(LFLAGS) @ echo "Link Success!" $(DIR_BUILD) $(DIR_BUILD_SUB): $(MKDIR) $@ clean: @ echo "Begin to clean." $(RM) $(DIR_BUILD) @ echo "Clean Success!" Rebuild: clean all$ (MODULES): $(DIR_BUILD) $(DIR_BUILD) / $(MAKECMDGOALS) @ echo "Begin to compile $@" @ set-e;\ for dir in $(MODULES) \ do\ cd $@ & &\ $(MAKE) all\ DEBUG:=$ (DEBUG)\ DIR_BUILD:=$ (addprefix $(DIR_PROJECT) /, $(DIR_BUILD))\ DIR_COMMON_INC:=$ (addprefix $(DIR_PROJECT) /, $(DIR_COMMON_INC))\ CMD_CFG:=$ (addprefix $(DIR_PROJECT) / (CMD_CFG))\ MOD_CFG:=$ (addprefix $(DIR_PROJECT) /, $(MOD_CFG))\ MOD_RULE:=$ (addprefix $(DIR_PROJECT) /, $(MOD_RULE)) & &\ cd. ;\ done @ echo "Compile Success!"

Let's take a look at the compilation results.

We see that the common module has been compiled correctly and the corresponding common.a file has been generated. Let's continue to compile the other two modules and use the linked command to see if the executable program app.out can be generated.

We see that the executable program app.out has been generated correctly. So we see that the module writing just now is to directly copy the previous code, and when it comes to copying and pasting code, we have to see if it can be encapsulated in a form similar to a function. The code reuse rules in makefile are like this. When a large number of commands in different rules are repeated, you can consider custom functions. Custom functions in makefile are a way of code reuse. As follows

The specific ideas are: 1, the command of the compilation module as the specific implementation of the custom function; 2, the function parameter is the module name, the module specified by the compilation parameter after the function call; 3, call the function in different rules. As follows

Let's see what the changed makefile looks like, changing the previous pro-rule.mk to the following

.PHONY: all compile link clean rebuild $(MODULES) DIR_PROJECT: = $(realpath.) DIR_BUILD_SUB: = $(addprefix $(DIR_BUILD) /, $(MODULES)) MODULE_LIB: = $(addsuffix .a, $(MODULES)) MODULE_LIB: = $(addprefix $(DIR_BUILD) /, $(MODULE_LIB)) APP: = $(addprefix $(DIR_BUILD) / (APP)) define makemodule cd ${1} & &\ $(MAKE) all\ DEBUG:=$ (DEBUG)\ DIR_BUILD:=$ (addprefix $(DIR_PROJECT) /, $(DIR_BUILD))\ DIR_COMMON_INC:=$ (addprefix $(DIR_PROJECT) /, $(DIR_COMMON_INC))\ CMD_CFG:=$ (addprefix $(DIR_PROJECT) / (CMD_CFG))\ MOD_CFG:=$ (addprefix $(DIR_PROJECT) /, $(MOD_CFG))\ MOD_RULE:=$ (addprefix $(DIR_PROJECT) /, $(MOD_RULE)) & &\ cd. ; endefall: compile $(APP) @ echo "Success! Target = > $(APP)" compile: $(DIR_BUILD) $(DIR_BUILD_SUB) @ echo "Begin to compile." @ set-e;\ for dir in $(MODULES);\ do\ $(call makemodule, $dir)\ done @ echo "Compile Success!" Link $(APP): $(MODULE_LIB) @ echo "Begin to link..." $(CC)-o $(APP)-Xlinker "- (" $^-Xlinker "-)" $(LFLAGS) @ echo "Link Success!" $(DIR_BUILD) $(DIR_BUILD_SUB): $(MKDIR) $@ clean: @ echo "Begin to clean." $(RM) $(DIR_BUILD) @ echo "Clean Success!" Rebuild: clean all$ (MODULES): $(DIR_BUILD) $(DIR_BUILD) / $(MAKECMDGOALS) @ echo "Begin to compile $@" @ set-e;\ $(call makemodule, $@)

The result of the compilation is

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