Shulou(Shulou.com)11/24 Report--

On August 28, CTOnews.com, Bao Yungang, a researcher at the Institute of Computing Technology of the Chinese Academy of Sciences, announced that on August 24, 2022, the Institute of Computing of the Chinese Academy of Sciences, Beijing Open Source Chip Research Institute, Tencent, Ali, ZTE, Yiswei, and Maneng formed a joint R & D team to carry out the joint development of the third generation Xiangshan (Kunming Lake architecture).

Xiangshan uses lakes to name each generation of architecture-the first generation architecture is Yanqi Lake, the second generation architecture is Nanhu, and the third generation architecture is Kunming Lake. Xiangshan open source community said that the first generation of "Yanqi Lake" architecture has been successfully filmed, measured to achieve the expected performance, the second generation of "South Lake" architecture is in continuous iterative optimization.

CTOnews.com learned that Xiangshan is an open source RISC-V processor core, "Nanhu" uses SMIC 14nm technology, the target frequency is 2GHz DDR CPU score of 10 points / GHz, support dual-channel SPEC memory as well as PCIe, USB, HDMI and other functions.

According to reports, one of the important decisions in the development of the "Xiangshan" processor core is to choose the agile design language Chisel, because the development efficiency is much higher than that of Verilog and achieves the same function, and the amount of Chisel code is only 1 amp 5 of Verilog.

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