China's first Native Chiplet small Chip Technology Standard released
CTOnews.com news on December 16, at today's "second China Interconnection Technology and Industry Conference", the first group standard of "small chip interface bus technical requirements" led by relevant enterprises and experts in the field of integrated circuits in China was formally approved and issued by the China Electronics Industry Standardization Technology Association of the Ministry of Industry and Information Technology.
According to reports, this is China's first native Chiplet technical standard.
In May 2021, China computer Interconnection Technology Alliance (CCITA) established the Chiplet standard in the Ministry of Industry and Information Technology, namely "Technical requirements for small Chip Interface bus". The standard formulation work was carried out jointly by the Institute of Computing of the Chinese Academy of Sciences, the fourth Institute of Electronics of the Ministry of Industry and Information Technology and a number of domestic chip manufacturers.
CTOnews.com once reported that on March 28 this year, the China computer Interconnection Technology Alliance (CCITA) Joint Institute of Electronic Standards, a number of enterprises, and scientific research institutes jointly formulated the "Technical requirements for small Chip Interface bus" and "Microelectronic Chip Optical Interconnection Interface Technology", which completed the draft standard and began to solicit opinions from the community.
"small Chip Interface bus Technical requirements" describes the small chip interface bus (chip-let) technical requirements for CPU, GPU, artificial intelligence chips, network processors and network switching chips, including general overview, interface requirements, link layer, adaptation layer, physical layer and packaging requirements.
According to reports, the small chip interface technology has the following application scenarios:
C2M (Computing to Memory), the interconnection between computing chip and memory chip.
C2C (Computing to Computing), the interconnection between computing chips. How to connect the two:
It adopts parallel single-ended signal connection, which is mostly used for the interconnection of multiple computing chips in CPU.
Serial differential signal connection is used to expand the performance of AI and Switch chips.
C2IO (Computing to IO), the interconnection of computing chips and IO chips.
C2O (Computing to Others), the interconnection of computing chips and other small chips such as signal processing and baseband units.
This standard lists three kinds of interfaces, such as parallel bus, puts forward a variety of speed requirements, and the total connection bandwidth can reach 1.6Tbps, in order to flexibly respond to different application scenarios and technology suppliers with different capabilities. Through the detailed definition of link layer, adaptation layer and physical layer, the interconnection and interworking between small chips is realized, and the requirements for encapsulation are listed, taking into account the support of existing protocols such as PCIe. Small chip design can not only use international advanced packaging methods, but also make full use of the accumulation of domestic packaging technology.
An overview of the standard of "small chip interface bus technology"
