Shulou(Shulou.com)11/24 Report--

CTOnews.com, December 28, Intel engineer Huang Ying today released a patch set that enables batch TLB refresh of page migration in the migrate_pages () function and is outstanding in terms of performance optimization.

CTOnews.com learned that migrate_pages () is responsible for page migration (Page Migration) in Linux Kernel, while page migration can specify the pages of a process to its specified memory node. It is designed to reduce memory access latency by moving pages to the NUMA node where the process is located. This feature was later used in scenarios such as regular memory and hot-swappable memory.

After the migrate_pages () function received multiple pages, Intel engineers worked hard to support batch processing of TLB refresh and replication while reducing the number of interprocessor interrupts (IPI).

TLB (translation lookaside buffer) can be thought of as a cache. Data cache cache address (virtual address or physical address) and data. TLB caches virtual addresses and their mapped physical addresses. TLB looks for cache based on the virtual address. It has no choice but to look up the virtual address. So TLB is a virtual cache.

The migrate_pages () function is used to move all pages in the process to another set of nodes. The patch series also allows the use of Intel data flow Accelerator (DSA) on Xeon Scalable Sapphire Rapids processors.

After installing the patch, the migrate_pages () test results showed that IPI decreased by 99.1% during the test period, and the number of pages successfully migrated per second increased by 291.7%.

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