Marvell Meiman launches 51.2 Tbps programmable switch chip Teralynx 10, which is based on 5nm

Thanks to CTOnews.com netizen OC_Formula for the clue delivery! CTOnews.com March 6 news, Marvell Electronics (Marvell) last week launched a programmable switch chip Teralynx 10, which claims to be "the lowest latency in the industry". This is a 51.2T switch chip specially designed for the 800GbE era.

This is a 51.2 Tbps programmable 5nm chip designed to solve the problem of bandwidth explosion among operators while meeting stringent power consumption and cost requirements. It is suitable for leaf and spine applications in next-generation data center networks, as well as AI / ML and high-performance computing (HPC) structures.

According to reports, one Teralynx 10 is equivalent to 12 12.8 Tbps first-generation chips, thus reducing power consumption by 80 per cent at the same capacity.

Teralynx 10 has 512 long reach (LR) 112G SerDes and has the lowest bit error rate (BER) in the industry. With it, switch systems can develop more comprehensive switch configurations, such as 32 x 1.6T, 64 x 800G, and 128 x 400G links, giving vendors the flexibility to meet the unique needs of each operator.

It adopts ultra-low latency structure, is compatible with Teralynx software, and supports Teralynx Flashlight advanced telemetry technology, including P4 in-band network telemetry (INT).

According to reports, the Teralynx 7 generation switch has shipped about 5 million 400GbE ports, and Teralynx 10 will provide samples in the second quarter.

CTOnews.com to explain briefly here, the existing PCIe Gen5 speed only supports 400GbE links, and it is not expected to see 800GbE or higher mainstream servers and storage devices until 2-3 years later when PCIe Gen6 is available.