Without changing the process to reduce the chip area by 30%, Samsung set up a team to develop 4FMC178; DRAM.

Thanks to CTOnews.com netizen OC_Formula for clue delivery! CTOnews.com May 26 news, according to South Korean media The Elec reported that Samsung formed a professional team responsible for the development of 4F² DRAM memory cell structure. Compared to the existing 6F ² class, the chip area can be reduced by up to 30% without changing the process node.

4F Square is a cell structure technology that the DRAM industry tried to commercialize as early as 10 years ago, but it ended in failure.

Samsung formed a professional team to develop the 4F² structure. CTOnews.com learned from Korean media reports that transistors form a complete system of source (S), gate (G) and drain (D) according to the direction of current inflow and outflow.

Above the drain (D), a capacitor for storing charge is mounted, and the transistor contacts the horizontally arranged WL line and the vertically arranged BL line, where WL is connected to the gate (G) and is responsible for turning the transistor on/off, and BL is connected to the source (S) and is responsible for reading and writing data.