Shulou(Shulou.com)11/24 Report--

Thanks to CTOnews.com netizens Wu Yanzu and OC_Formula for the clue delivery! CTOnews.com, September 10 (Xinhua)-- AMD's fifth-generation EPYC processor "Turin" will continue to use the existing SP5 platform, which is in line with the policy that the two-generation AMD server CPU will use the same slot, while its successor, "Venice", is expected to use a new SP7 platform.

@ Jiecheng Ansui-YuuKi_AnS has obtained AMD's latest data center roadmap, AMD's sixth-generation EPYC processor code-named "Venice", which is based on the next-generation Zen 6 core and will use a brand new SP7 slot.

He asserts that the new platform will support up to 16 memory channels, DDR5 and new memory (such as MR-DIMM and MCR-DIMM), even if the new processor has hundreds of cores.

Given the increase in the number of cores, we expect the new SP7 platform to bring significant power enhancements to Venice processors, and we expect significant improvements in AMD sixth-generation EPYC processors, given that SP5 can power up to 700W.

However, we still know very little about SP7 processors, considering that SP5 has 6096 pins, so we can assume that the new platform will use more pins, and may also use larger CPU encapsulation, thus increasing the number and functionality of cores.

Zen3Zen4Zen5Zen6 code 7003 "Milan (- X)" 9004 "Genoa (- X)"

8004 "Bergamo"

8004 "Siena" 9005 "Turin (- X)"

8005 "Turin-Dense" 9006 "Venice" date 202120232024025+ platform SP3 (LGA4094) SP5 (LGA-6096)

SP6 (LGA 4094) SP5 (LGA-6096)

SP6 (LGA 4094) SP7 Core 64C96C/128C128C/192CTBC memory 8C DDR412C DDR512C DDR516C DDR5

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