It is reported that Samsung Exynos 2400 chip will adopt FOWLP packaging process: smaller size, stronger performance and lower power consumption.

CTOnews.com, November 15, according to South Korean media EDaily, Samsung has completed the verification of the fan-out wafer-level packaging (FOWLP) process and has begun to deliver products to customers, and the first chip using this packaging process will be the Exynos 2400 chip to be installed in Galaxy S24 / S24 + phones next year.

CTOnews.com reported in April that Samsung plans to use FOWLP technology for Exynos 2400 processors in order to catch up with Qualcomm Snapdragon.

FOWLP technology is considered to be the key technology to improve the performance of semiconductor chips, and it is also one of the important magic weapons for Samsung to catch up with TSMC.

It is reported that Samsung Electronics is actively promoting the FOWLP process, which will be used in large-scale mass production of chips.

At present, the mainstream of semiconductor chip packaging requires chips to connect to PCB (printed circuit board) to stack them, while FOWLP does not need PCB, because the chip is directly connected to the wafer.

Compared with the currently used FC-BGA (Flip Chip-Ball Grid Array) chip packaging technology, the size of the chip using FOWLP is reduced by 40%, the thickness is reduced by 30%, and the performance is improved by 15%. The technology has been used to make GDDR6W chips launched at the end of last year.

Based on previous information, the Exynos 2400 processor uses a 1-2-3-4 design:

1 Cortex-X4 core with 3.1GHz clock rate

2 Cortex-A720 cores with 2.9GHz clock rate

3 Cortex-A720 cores with 2.6GHz clock rate

4 Cortex-A520 cores with 1.8GHz clock rate

Exynos 2400 will use a RDNA2 GPU named Xclipse X940 (tentative), which contains 6 WGP (12 CU), 8 MB L3 cache, and supports hardware-level RayTracing.

Related readings:

Samsung catches up with Qualcomm Snapdragon, sources say the Exynos 2400 processor is packaged in FoWLP.