Shulou(Shulou.com)11/24 Report--

CTOnews.com, November 4, CTOnews.com recently released the first independently developed EDA tool-- EnFortius Low Power Checker (referred to as LPC). LPC is mainly used for static verification of low-power designs and can quickly locate possible design loopholes and defects caused by low-power designs for integrated circuit (IC) engineers.

Inoda's EnFortius series of tools is designed to solve the low-power design problems faced by chip design engineers, and the release of LPC is the first in the series. Many years ago, in order to meet the needs of low-power design, the industry gave birth to a design standard for optimizing power consumption, which is now the IEEE-1801 standard, also known as the unified low-power design format (UPF). Due to the rapid update of low-power design methodology, IEEE-1801 has experienced four major updates since the first version was launched in 2008. The compatibility between different versions makes it one of the most difficult standards to support in the field of EDA.

CTOnews.com learned that Inoda LPC adopts a new product architecture and builds the core power intention data structure based on the latest UPF3.1 information model, which can help IC design engineers build a customized static verification process based on LPC.

Yinoda (Chengdu) Electronic Technology Co., Ltd. is a local EDA company. In order to improve the efficiency of chip design and solve the problem of a large number of computing resources needed for system-level chip verification, Inoda established the first EDA hardware verification cloud platform exclusively authorized by Cadence. Inoda's main business also includes: chip design services based on complete solutions and digital mid-range EDA software with fully independent intellectual property rights. The company's long-term goal is to explore the path and model of industrial software cloud based on China's national conditions through the practice of EDA hardware and software cloud, relying on the research and development of local EDA software and IP, so as to enable the high-quality development of the semiconductor industry.

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