Die Shot diagrams and performance indicators of Intel Emerald Rapids Xeon processors exposed

CTOnews.com, December 6, news source @ InstLatX64 recently disclosed an Intel document sharing more information about Emerald Rapids processors.

Intel plans to launch the Xeon 5 processor codenamed Emerald Rapids on December 14, using the same sockets and platforms as Sapphire Rapids.

Die-shot figure exposure Intel introduces the Emerald Rapids processor in this document, which is produced by the Intel 7 process.

Emerald Rapids processors are equipped with Raptor Cove cores, which can encapsulate up to 64 cores at a time. Unlike Sapphire Rapids, the tile structure architecture is that Emerald Rapids is 2 tiles; and Sapphire Rapids is 4 tiles.

In terms of CPU layout, two cores are connected to the cache array through Modular Die Fabric, with a total of four memory controllers, supporting up to 8 channels of DDR5-5600 memory.

In addition, there are 6 PCIe controllers, 4 UPI channels and 4 accelerator engines between the two die.

CTOnews.com Note: Emerald Rapids has significantly improved the cache structure, and Intel's L3 cache capacity has increased from the largest 112.5MB to the highest 448MB. In addition, 2MB's L2 cache is reserved for each core.

In order to make a significant difference between the fourth-generation and fifth-generation Xeon products, Intel compared the two series of flagship products.

Including Sapphire Rapids-based 8480 cycles, there are 56 cores, while 8592 + has 64 cores and has more L3 caches.

In various benchmarks, Intel does promise to make a big leap in performance.

It is worth noting that Emerald Rapids's successor, Granite Rapids, is expected to bring huge improvements in efficiency and performance.

Granite Rapids is scheduled to be launched in 2024 and will be manufactured using the Intel 3 (3nm level) process Redwood Cove P core. It is expected to equip the SP variant with 88 cores and the AP variant with 132 cores.