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Intel's latest technology shows that by combining 3D stacked CMOS transistors with back power and back contacts, CFET is realized under 60nm gate distance for the first time.

2024-02-29 Update From: SLTechnology News&Howtos shulou NAV: SLTechnology News&Howtos > IT Information >


Shulou( Report--

Thanks to netizen knsgccxr for the clue delivery! December 10 news, due to the current slowdown of Moore's Law, the concept of stacked transistors has regained its attention. IMEC (Belgian Microelectronics Research Center) proposed a miniature version of CFET technology for stacking complementary transistors in 2018 ( Note: vertical stacking complementary field effect transistor technology, the industry believes that CFET will replace full-gate GAA transistor technology), Intel and TSMC have also followed.

At this year's IEEE International Electronic Devices Conference (IEDM 2023), Intel demonstrated a number of technological breakthroughs and emphasized the continuation and evolution of Moore's Law.

First, Intel demonstrated a breakthrough in 3D stacking CMOS (complementary metal oxide semiconductor) transistors.

Simply put, researchers have achieved the industry's first CFET with a reduced gate spacing of 60 nm by combining 3D stacked CMOS transistors with back power and rear contact technology.

▲ Intel schematic in addition, the company reported on the expansion path of recent R & D breakthroughs in back power technology, such as back contacts (backside contacts), and demonstrated for the first time the implementation of large-scale integrated silicon transistors and gallium nitride (GaN) transistors on the same 300mm wafer (as opposed to the same package).

Intel is also a breakthrough in the expansion of its next-generation transistors for future nodes, thus continuing the concept of Moore's Law again.

In addition to improving back power supply and adopting novel two-dimensional channel materials, Intel is committed to achieving its goal of "extending Moore's Law to include a trillion transistors in a single package by 2030."

Recently, Intel also announced its latest process technology roadmap, highlighting the company's innovations in continued expansion, including power on the back of the PowerVia, as well as glass substrates and Foveros Direct for advanced packaging, which are expected to go into production this decade.

Intel said this highlighted its leadership in full-gate transistors and demonstrated its ability to innovate outside of RibbonFET, putting it further ahead of its competitors.

"as we enter the Angstrom era and set the goal of four years and five nodes, continuous innovation has become more critical than ever," said Sanjay Natarajan, senior vice president and general manager of component research at Intel. At IEDM 2023, Intel demonstrated its progress in advancing Moore's Law, highlighting our ability to provide further expansion and efficient power for the next generation of mobile computing. "

Intel believes that it has exceeded its goal of "four years and five nodes" and has identified key areas of research and development needed to continue to use back power technology for transistor expansion:

Intel PowerVia will be ready for production in 2024, the first time the industry has achieved back power supply. At IEDM 2023, component Research identified ways to continue and expand back power supply technologies beyond PowerVia, as well as the key process advances needed to achieve these approaches. In addition, this work emphasizes the use of back contacts and other novel vertical interconnection techniques to achieve more efficient device stacking.

On IEDM 2022, Intel focuses on performance enhancements and building a viable 300mm GaN-on-silicon wafer path. This year, the company is promoting the integration of silicon and GaN processes. Intel has now successfully demonstrated a high-performance large-scale integrated circuit solution called DrGaN for power transmission. Intel researchers are the first to demonstrate that the technology performs well and has the potential to enable power transmission solutions to keep up with the power density and efficiency requirements of future computing.

Transition metal disulfide (TMD) two-dimensional channel materials provide a unique opportunity to reduce the physical gate length of transistors below 10nm. At IEDM 2023, Intel will demonstrate prototypes of high mobility TMD transistors, including NMOS (n-channel metal oxide semiconductors) and PMOS (p-channel metal oxide semiconductors), the key components of CMOS. Intel also showed the world's first full-gate surround (GAA) two-dimensional TMD PMOS transistor and the world's first two-dimensional transistor built on a 300mm wafer.

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