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Today to talk with you about Verilog how to achieve even, odd, half-integer, fractional frequency division and circuit diagram with D trigger to achieve frequency division, many people may not quite understand, in order to let you better understand, Xiaobian summed up the following content, I hope you can get something according to this article.

Usually we say N-frequency division of the original clock, that is, one cycle of the clock after frequency division is N times that of the original clock. N can be even, odd, semi-integer, fractional (decimal).

1. Even number frequency division

Verilog:N is an even number, and a counter cycle 0-(Nmur1) is used to count, and the output is inverted in Nmax 2-1 and Nmai 1 respectively, that is, N frequency division is completed.

If a D flip-flop is used to draw a frequency divider, the reverse output of a single D flip-flop to the input constitutes a simple 2-divider. On this basis, the frequency division output of the D flip-flop is used as the clock of the next D flip-flop. So in series, x series is 2 ^ x frequency division, which belongs to even frequency division, as shown in figure 1 [1].

Figure 1 Frequency division with D flip-flop

two。 Odd number frequency division

Verilog:N is odd, counting using a counter cycle 0-(Nmur1), controlling (NMU1) / 2 high levels, (Numb1) / 2 low levels, called A; then delaying this A level signal for half a clock cycle is called B, and finally outputting C = A | B, that is, an odd frequency divider with a duty cycle of 50%. The other option is (Numb1) / 2 high levels, (Nmur1) / 2 low levels, then the final output C=A&B.

Taking C = A | B as an example, there are two ways to delay A for half a clock cycle. method 1 is to directly use the latch of falling edge to latch A to get B. the principle of method 2 is the same as that of A. however, it is in the falling edge detection (assuming An is rising edge detection).

Fig. 2 Odd frequency division waveform

Using D flip-flop, using method 1, a D flip-flop with a falling edge is used to latch A=clkp1 to get the signal B=clkn1, and the frequency division clock signal clkout with 50% duty cycle is obtained by doing logic "and" between signal An and signal B.

Fig. 3 Odd frequency division

The following is the design of a frequency divider in which N is a positive integer. The main principle is that N [0] = 1 is odd and 0 is even.

Module practice_demo (input clk, input arst, output clk_div); parameter N = 5 X Reg [2:0] cnt;reg clk_a;reg clk_b;wire clk_c; always@ (posedge clk or posedge arst) begin if (arst) cnt

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