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AMD EPYC "Turin" CPU exposure: using Zen 5 + Zen 5C mixed design, 128core 256thread

2024-11-04 Update From: SLTechnology News&Howtos shulou NAV: SLTechnology News&Howtos > IT Information >

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CTOnews.com news on December 17, @ Jiecheng Ansui-YuuKi_AnS released photos of Turin, an AMD EPYC processor based on Zen5 architecture.

Judging from the figure, the design of this generation of processors has not changed much, with little change compared to the Genoa, except that the color of the bracket has changed and is expected to be compatible with the SP5 platform.

The series of processors has a maximum of 16 CCD, each CCD with 8 physical cores and a separate 32 MB L3 cache, a maximum of 128cores and 256threads, and a 512 MB L3 cache. Compared to the Genoa series CPU based on Zen 4, this series of processors increases the number of cores by 33% and L3 cache by 33%.

In addition, the processor IOD will feature an DDR5 integrated memory controller that supports 6000 MT/s speeds, as well as PCIe Gen5 (CXL 2.0), Gen3 Infinity Fabric and security processor support, as well as a range of other controllers and accelerators.

Turin is part of AMD's fifth-generation EPYC product line and will be used to replace the current fourth-generation EPYC family products (Genoa, Genoa-X, Bergamo and Siena). Considering that the fourth-generation EPYC processor (9004Univer 8004) uses a hybrid architecture of Zen 4 + Zen 4C, while the fifth-generation EPYC will use a similar Zen 5 (Nirvana) + Zen 5C (Prometheus) design.

Judging from the pictures given by @ Ansui-YuuKi_AnS, this Turin ES2 chip was produced in 2023 and looks very new.

In fact, @ Ditto_55 gave the OPN code for this series of processors (internal code Breithorn) last month, and the CTOnews.com is summarized as follows:

100-000001245-16 CCD + 1 IOD (128x Zen 5 core 256threads 512MB cache)

100-000001341-12 CCD + 1 IOD (96 Zen 5 core 192 threads 384 MB cache)

100-000001247-8 CCD + 1 IOD (64 Zen 5 core 128threaded 256MB cache)

100-000001342-8 CCD + 1 IOD (64 Zen 5 core 128threaded 256MB cache)

100-000001249-2 CCD + 1 IOD (32 Zen 5C cores 64 threads 64 MB cache)

Compared to the Zen 5 CCD, each Zen 5C CCD provides up to 16 cores and 32 MB L3 cache, plus 6 compute chips, achieving a total of 192 physical cores and 256 logical threads, but the L3 cache is only 384 MB and will retain the same I / O modules as other chips.

Compared with the Bergamo series CPU based on the Zen 4C core, the number of Turin chip cores and threads with the Zen 5C core will increase by 50% (192 MB 384 vs. 128 MB 256), and the number of caches will also increase by 50% (384 MB pairs and 256 MB).

AMD has confirmed that the Turin CPU based on the Zen 5 architecture will be launched in 2024 and will bring stronger performance per unit power consumption to counter the next generation of Intel Granite Rapids Xeon chips.

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